View ICS9279-03_248960.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS9279-03
Preliminary Product Preview
Low Skew Fan Out Buffers
General Description
The ICS9279-03 generates low skew clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Outputs will handle up to 133 MHz clocks. An output enable is provided for testability. The device is a buffer with low output to output skew. This is a Fanout buffer device, not using an internal PLL. This buffer can also be a feedback to an external PLL stage for phase synchronization to a master clock. There are a total of ten outputs, sufficient for feedback to a PLL source and to drive four small outline DIMM modules (S.O. DIMM) at 2 clocks each. Or a total of ten outputs as a Fanout buffer from a common clock source. The individual clock outputs are addressable through I2C to be enabled, or stopped in a low state for reduced EMI when the lines are not needed.
Features

Ten High speed, low noise non-inverting buffers for (to 133 MHz), clock buffer applications. Output slew rate faster than 1.5V/ns into 20pF Supports up to four small outline DIMMS (S.O. DIMM). Synchronous clocks skew matched to 250 ps window on OUTPUTs (0:9). I2C Serial Configuration interface to allow individual OUTPUTs to be stopped low. Multiple VDD, VSS pins for noise reduction Tri-state pin for testing 3.0V 3.7V supply range 28-pin (209 mil) SSOP package
Block Diagram
Pin Configuration
28-Pin SSOP
PentiumPro is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9279-03 Rev B 2/1/99
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9279-03
Preliminary Product Preview
Pin Descriptions
PIN NUMBER 2, 3 6, 7 22, 23 26, 27 11 18 9 20 14 15 1, 5, 10, 19, 24, 28 4, 8, 12, 16, 17, 21, 25 13 16 P I N NA M E OUTPUT (0:1) OUTPUT (2:3) OUTPUT (4:5) OUTPUT (6:7) OUTPUT8 OUTPUT9 BU F _ I N OE SDATA SCLK VDD (0:5) GND (0:5) VDDI GNDI TYPE OUT OUT OUT OUT OUT OUT IN IN I/O I/O PWR PWR PWR PWR DESCRIPTION C l o c k o u t p u t s 1, u s e s V D D 0 , G N D 0 C l o c k o u t p u t s 1, u s e s V D D 1 , G N D 1 Clock outputs1 uses VDD2, GND2 Clock output1 uses VDD3, GND3 Clock output1 uses VDD4, GND4 Clock output1 uses VDD5, GND5 Input for buffers Tri-states all outputs when held LOW. Has internal pull-up.2 D a t a p i n f o r I 2C c i r c u i t r y 3 C l o c k p i n f o r I 2C c i r c u i t r y 3 3.3V Power supply for OUTPUT buffers Ground for OUTPUT buffers 3.3V Power supply for I2C circuitry and internal logic G r o u n d f o r I 2C c i r c u i t r y a n d i n t e r n a l l o g i c
Notes: 1. At power up all ten OUTPUTs are enabled and active. 2. OE has a 100K Ohm internal pull-up resistor to keep all outputs active. 3. The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for complete platform flexibility.
Power Groups
VDD (0:5), GND (0:5) = Power supply for OUTPUT buffer VDDI, GNDI = Power supply for I2C circuitry
2
ICS9279-03
Preliminary Product Preview
Technical Pin Function Descriptions
VDD This is the power supply to the internal core logic of the device as well as the clock output buffers for OUTPUT (0:9). This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. OUTPUT (0:9) These Output Clocks are use to drive Dynamic RAMs and are low skew copies of the CPU Clocks. The voltage swing of the OUTPUTs output is controlled by the supply voltage that is applied to VDD of the device, operates at 3.3 volts. I2C The SDATA and SCLOCK Inputs are use to program the device. The clock generator is a slave-receiver device in the I2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I2C specification in Philips I2C Peripherals Data Handbook (1996) should be followed. BUF_IN Input for Fanout buffers (OUTPUT 0:9). OE OE tristates all outputs when held low. VDD1 This is the power supply to I2C circuitry.
3
ICS9279-03
Preliminary Product Preview
General I2C serial interface information
A. For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with an acknowledge bit between each byte.
Clock Generator Address (7 bits) A(6:0) & R/W# D2(H) ACK + 8 bits dummy command code + 8 bits dummy Byte count
ACK
ACK
Then Byte 0, 1, 2, etc in sequence until STOP.
B.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB PIIX4 protocol.
Clock Generator Address (7 bits) A(6:0) & R/W# D3(H) ACK Byte 0 ACK Byte 1 ACK
Byte 0, 1, 2, etc in sequence until STOP.
C. D. E. F.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches maintain all prior programming information. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default to a 1 (Enabled output state).
G . H.
Serial Configuration Command Bitmaps
Byte 0: OUTPUT Clock Register (Default=0)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PIN# 7 6 3 2 PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d OUTPUT3 OUTPUT2 OUTPUT1 OUTPUT0
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
4
ICS9279-03
Preliminary Product Preview
Functionality
OE# 0 1
OUTPUT (0:9) Hi-Z 1 X BUF_IN
Byte 1: OUTPUT Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 27 26 23 22 PWD 1 1 1 1 1 1 1 1 DESCRIPTION OUTPUT7 (Act/Inact) OUTPUT6 (Act/Inact) OUTPUT5 (Act/Inact) OUTPUT4 (Act/Inact) R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Byte 2: OUTPUT Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 18 11 PWD 1 1 1 1 1 1 1 1 DESCRIPTION OUTPUT9 (Act/Inact) OUTPUT8 (Act/Inact) R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
ICS9279-03 Power Management
The values below are estimates of target specifications.
Max 3.3V supply consumption Max discrete cap loads VDD = 3.465V All static inputs = VDD or GND 3mA
Condition
No Clock Mode (BUF_IN - VDD1 or GND) I2C Circuitry Active Active 66MHz (BUF_IN = 66.66MHz) Active 100MHz (BUF_IN = 100.00MHz)
230mA 360mA
5
ICS9279-03
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current SYMBOL VIH VIL IIH IIL IIL IDD1 IDD2 IDD3 IDD4 Fi 1 CIN1 CONDITIONS MIN 2 VSS-0.3 -5 -60 TYP MAX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 120 mA 180 mA 260 mA 360 mA 133 5 MHz pF
Operating Supply Current Input frequency Input Capacitance
1
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with 100K pull-up resistors CL = 0 pF; FIN @ 66M CL = 0 pF; FIN @ 100M CL = 30 pF; RS=33; FIN @ 66M CL = 30 pF; RS=33; FIN @ 100M VDD = 3.3 V; All Outputs Loaded Logic Inputs
-33 80 120 180 240
10
Guarenteed by design, not 100% tested in production.
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
6
ICS9279-03
Preliminary Product Preview
Electrical Characteristics at 3.3V
VDD = 3.0 3.7 V, TA = 0 70 C unless otherwise stated
Electrical Characteristics - Outputs
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1
SYMBOL RDSP RDSN VOH VOL IOH IOL Tr Tf Dt Tsk TPROP1 TPROP2
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -30 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 50% BIN to 10% OUT VT = 1.5 V VT = 1.5 V
MIN 10 10 2.6
TYP
40
3 0.27 -115 57 0.95 0.95
MAX UNITS 24 24 V 0.4 V -54 mA mA 1.33 1.33 55 250 5.5 5 8 8 ns ns % ps ns ns ns ns
Duty Cycle
45 1 1 1 1
51 110 5.2 4.3
Propagation
1
1
TPROPEN TPROPDIS
Guarenteed by design, not 100% tested in production.
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
7
ICS9279-03
Preliminary Product Preview
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs.
Capacitor Values: All unmarked capacitors are 0.01F ceramic
8
ICS9279-03
Preliminary Product Preview
SYMBOL MIN. A A1 A2 b c D E e H L N 0.068 0.002 0.066 0.010 0.004 0.205 0.301 0.025 0
COMMON DIMENSIONS NOM. 0.073 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4 MAX. 0.078 0.008 0.070 0.015 0.008 0.212 0.311 0.037 8
VARIATIONS N 28 MIN. 0.397
D NOM. 0.402 MAX. 0.407
Dimensions in inches
Ordering Information
ICS9279F-03
Example:
209 mil 28 Pin SSOP Package
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
9
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

▲Up To Search▲

Price & Availability of ICS9279-03

	To Download ICS9279-03 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .